Secure 32-bit RISC Processor

The S8 is a secure processor based on a 32-bit RISC architecture specifically optimized for embedded applications. Its low gate count structure operates from a compact code size while achieving high performances on Linux VM, Java VM or OpenSSL library.

Key Features

​Secure architecture
High code density
Small gate count
Low power consumption
Silicon proven

Features


Architecture
  • Harvard bus architecture​
  • 4-stage pipeline
  • registers:
    • 16 general purpose registers
    • 2 operating system reserved registers
    • 3 debug registers
    • 3 trap registers
  • characteristics of three 65 nm implementations (fmax / gatecount / area):
    • high-speed: 1900 MHz / 18830 gates / 0.039 mm²
    • trade-off: 1000 MHz / 13781 gates / 0.029 mm²
    • low-area: 333 MHz / 12742 gates / 0.026 mm²
  • AHB bus protocol compliant
  • unaligned memory access supported
Security
  • code obfuscation by instruction re-encoding
  • possibility to define new instructions
  • User and Supervisor modes
  • illegal opcode detection
  • tamper-resistant registers
  • non-maskable interrupts
  • enhanced dynamical bus encryption
  • encrypted CPU data registers
  • instruction execution time independent from data value
  • random execution time
  • optional countermeasures through external hardware IPs:
    • strong memory encryption
    • ARIM IP: protection against code re-routing
    • SEC IP: secure boot
Instruction set
  • proprietary instruction set
  • customizable opcode encoding
  • opcode available for custom instructions
  • ultra-compact code size
  • instruction length from 1 to 6 bytes
  • code size smaller than Thumb or 8051
  • instructions adapted to embedded applications
Performances
  • high performances:
    • Dhrystone score: 1.2 DMIPS/MHz
    • CoreMark score: 2.0
  • high code-density:
    • code size ratio = 75% versus Thumb-2
  • low power consumption:
    • few stack accesses, optimized Application Binary Interface (ABI)
    • few fetch accesses, 2 byte long instructions on average​​
    • multilevel gated clock methodology
    • wait for interrupt instruction
    • Low Power Polling function (LPP)
Development tools
  • compiler:
    • cross compilation of GCC 4.7.2
    • GCC backend and Binutils
    • Link Time Optimization (LTO) supported
    • unaligned memory access supported
  • debugger:
    • based on GDB 7.5
    • Dwarf information supported
  • Integrated Development Environment (IDE):
    • Eclipse Indigo
  • emulator:
    • Altera Cyclone IV FPGA board
    • ISO paddle with voltage level translator

Deliverables

  • ​RTL:​
    • ​VHDL source codes​
    • Synopsys synthesis scripts
  • tools:
    • getting started manual​
    • Collection Tools manual
    • GCC, GDB and Eclipse documentations
  • emulator:​
    • Altera Cyclone IV FPGA board
    • ISO paddle with voltage level translator
  • specifications:
    • design specification
    • Instruction Set Architecture (ISA)
    • Application Binary Interface (ABI)

Please contact sales@invia.fr for any further information.