Laser Pulse Detector

​​The Laser Pulse Detector is a fully integrated mixed-signal IP detecting bit-flipping attacks.

Key Features

High sensitivity
Standard cell like
Ultra low power
Very compact
Easy integration


  • analog-based architecture packaged as a standard cell
  • straightforward integration within the digital logic area
  • full-custom layout optimized for an hyper sensitivity to laser pulses
  • detection threshold lower than bit-flipping energy levels​
  • form factor equivalent to that of 2.5 NAND2 gates
  • typical characteristics of a 55 nm CMOS implementation:
    • power supply voltage range: 1.2 V ±10%
    • operating junction temperature range: -40°C to 125°C
    • ​typical operating current smaller than 100 pA​
    • Y dimension: 1.4 µm (height of a standard cell)
    • X dimension: 1.8 µm (length of 2.5 NAND2 gates)
  • ​silicon proven in a 55 nm CMOS process
  • successfully evaluated by a security laboratory​


  • ​GDSII stream and layer map file
  • Library Exchange Format (LEF) file
  • Circuit Description Language (CDL) netlist
  • Liberty Timing File (.lib and .db)
  • VHDL behavioral model
  • design specification

Please contact for any further information.