ESD Protection

​The ESD Protection is a silicon-proven IP
supporting up to 8 kV HBM (Human Body Model)​.

Key Features

​8 kV HBM
1 kV CDM
Small area
Silicon proven​
Straightforward integration

Features

  • latch-up free 8 kV HBM ESD protection (JEDEC JESD22-A114E standard)
  • support up to 1 kV CDM (JEDEC JESD22-C101E standard)
  • ramp-up higher than 200 ns
  • noise time higher than 100 ns with 4 V peak-to-peak
  • operating junction temperature range: -40°C to +125°C
  • typical silicon area smaller than 0.05 mm²
  • silicon proven in 130 nm and 55 nm CMOS processes
  • validated on silicon by an independent laboratory (ISO 9001-2008)

Deliverables

  • GDSII stream and layer map file
  • Library Exchange Format (LEF) file
  • Circuit Description Language (CDL) netlist
  • design specification​

Please contact sales@invia.fr for any further information.