EPC Gen2 Analog Front End

​The EPC Gen2 Analog Front End (AFE) is a fully integrated analog IP intended for UHF Radio Frequency Identification (RFID) tags.

Key Features

​EPC Gen2 1.2.0 compliant
ISO 18000-6c compliant
High sensitivity level
Straightforward integration
Silicon proven


  • fully compliant with the EPC Gen2 1.2.0 standard
  • fully compliant with the ISO 18000-6c standard
  • contactless transmission of data and power
  • includes the antenna pads, a voltage multiplier, a Low DropOut (LDO) voltage regulator,
    a load modulator, a demodulator and an oscillator
  • straightforward integration through a standard interface (customized on request)
  • characteristics of a 130 nm CMOS implementation based on MIM capacitors:
    • generated supply voltage range (vdd): 1 V ±10%
    • voltage multiplier efficiency of 25%
    • -17 dBm sensitivity for a 5 µW power consumption
    • quiescent power consumption lower than 1.5 µW
    • input impedance: 40 - j400
    • operating junction temperature range: -40°C to +65°C
    • silicon area smaller than 0.07 mm²
  • silicon proven in a 130 nm CMOS process


  • GDSII stream and layer map file
  • Library Exchange Format (LEF) file
  • Circuit Description Language (CDL) netlist
  • Liberty Timing File (.lib)
  • VHDL behavioral model
  • design specification

Please contact sales@invia.fr for any further information.