​​​​The Anti-Fuse is a secure One-Time Programmable (OTP) memory
with redundant architecture and margin check mechanism.

Key Features

​​Redundant architecture
Margin-check mode
Secure mode
Low-power mode
Silicon proven


  • 32-bit OTP anti-fuse memory (size customized on request)
  • redundant architecture preventing from reading errors
  • margin check mode evaluating the anti-fuse state reliability
  • high-voltage manager controlling the external blowing voltage​
  • two operating modes:
    • secure mode protecting against bit-flip attacks
    • low-power mode reducing significantly the current consumption
  • ​​​operating junction temperature range: -40°C to 125°C
  • electrical characteristics of a 65 nm CMOS implementation:
    • power supply voltage range: 1.2 V ±10%
    • typical operating current lower than 100 µA
    • low-power mode operating current smaller than 1 µA
    • wake-up time shorter than 500 µs
    • silicon area smaller than 0.16 mm²
  • silicon proven in a 65 nm CMOS process


  • GDSII stream and layer map file
  • Library Exchange Format (LEF) file
  • Circuit Description Language (CDL) netlist
  • Liberty Timing File (.lib)
  • VHDL behavioral model
  • design specification

Please contact for any further information.