AES Coprocessor

The AES Coprocessor encrypts and decrypts 128-bit data blocks by computing AES algorithm with 128-bit keys through a highly optimized architecture.

Key Features

​Encryption & decryption
Key expander included
Fast on-the-fly computation
Low gate count​
Silicon proven

Features

  • AES decryption and encryption
  • key expander included
  • 128-bit data blocks
  • 128-bit keys
  • optional support of 192 and 256-bit keys​
  • less than 4.8 kgates
  • less than 110 ns for an on-the-fly AES computation
  • when used as CPU peripheral, the external clock is selected
  • when used as an on-the-fly encrypt/decrypt machine, an internal clock is used
  • AES computation in CRT and ECB modes through software-based scheduling
  • AMBA APB bus interface (customized on request)

Deliverables

  • VHDL source codes
  • VHDL test benches
  • Synopsys synthesis scripts
  • design specification

Please contact sales@invia.fr for any further information.