Infrastructure IPs is the bedrock of silicon security: secure processors, power managers and secure clock generators are the foundations of any secure platform.
The SoC Defender™ is a integrated Secure Element securing System on Chips and FPGAs. Our Root of Trust enab
The True Random Number Generator (TRNG) Digital Noise Source is a standard-cell based entropy generator
The Secure Clock Generator is a fully integrated mixed-signal IPsecuring the clocked system against side-channel attacks.
The True Random Number Generator (TRNG) Analog Noise Sourceis a physical entropy source compliant with the AIS 31 standard.
The True Random Number Generator (TRNG) Digital Post-Processingis a digital IP compliant with the AIS 31 and NIST SP 800-90B standards.
The Physical Unclonable Function (PUF) is a fully integrated analog IP generating a stable number from random local process variations.
The Power Manager is a fully-integrated Low-DropOut (LDO) voltage regulator intended to power secure System-on-Chip (SoC) platforms.
The Anti-Fuse is a secure One-Time Programmable (OTP) memorywith redundant architecture and margin check mechanism.
The Secure Crystal Oscillator is a fully integrated analog IP generatinga secure clock signal through the resonance of an external crystal.
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